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fxmelvin's avatar
fxmelvin
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4 years ago
Solved

Synthesis - Incorrect SystemVerilog interface parameter override

I have come across an issue where Quartus Pro (21.x) Synthesis incorrectly resolves an interface parameter to its default value rather than the value with which it should've been overridden by the in...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi @fxmelvin ,

    FYI. The bug had been fixed and implemented in Quartus Pro Edition version 22.4 internal build. Tested and worked fine check the image below:

    Kindly wait for the version release. Thank you for your patience.

    Thanks,

    Best Regards,
    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi @fxmelvin ,

The feature requested will be planned in version 22.3. A patch will be added to that particular version. These are the feedbacks from internal engineering.

Best regards,
Sheng


fxmelvin's avatar
fxmelvin
Icon for New Contributor rankNew Contributor
4 years ago

@ShengN_Intel This is issue hasn't been fixed in Quartus Pro 22.3.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    @fxmelvin Here is the latest update from internal team:

    Moving this to 22.4 due to schedule. Will work with Verific to provide a fix for this.