Forum Discussion
New ContributorSynthesis - Incorrect SystemVerilog interface parameter override
Hi @fxmelvin ,
FYI. The bug had been fixed and implemented in Quartus Pro Edition version 22.4 internal build. Tested and worked fine check the image below:
Kindly wait for the version release. Thank you for your patience.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Super ContributorHi,
I notice you use localparam for logic INIT_V in mem_if. Try don't to use that else DATA_W and ADDR_W will be assigned with local parameter. Delete the localparam and add INIT_V to modport mem will do.
Best regards,
Sheng
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
New ContributorThe original code is correct SystemVerilog usage and does not have to be changed; parameter dependence is a well understood aspect of SystemVerilog, having even a dedicated section in the standard explaining how overriding the relevant parameters during instantiation implies that the final parameter value must refer to that instead of any defaults.
Furthermore, if I understand what you're suggesting, i.e. have INIT_V as part of the mem.sv, that's not good enough for my use case; the example shared in this post is just a minimal, reproducible example of the original problem.
Lastly, note that the same code is synthesized correctly by other FPGA tools like Vivado.
- ShengN_altera
Hi @fxmelvin ,
I have read through your post and understand what you are asking for now. Anywhere, I'll reflect this particular problem to internal engineering for further ado. Thanks for your sharing.
Best regards,
Sheng
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
