StratixV transceiver simulation

When I say port I mean I take the old design and replace the StratixIV IP with StratixV IP leaving the architecture of the logic internal to the FPGA intact. If this was not done the design would fail to compile in Quartus since StratixIV transceivers are very different from StratixV transceivers.

The design compiles in Quartus and even functions on a real live StratixV FPGA. The only thing that does not work is the simulation model of the RX side of the transceiver.

What I will do today is to distill the project down into just the failing element by removing all the proprietary logic connected to the transceiver. That way I will have a small project that I can share.

I have stripped the project down into a 32M ZIP file. The only reason it is so big is because I included the Altera libraries for ModelSim that are created by the msim_setup.tcl script. I can remove these for those who already have their ModelSim environment set up with the StratixV libraries.

The simulation can be run with a few mouse clicks. I have a script which builds the IP libraries, compiles everything else, kicks off vsim and opens the Wave window.

Double-clock on the MPF to open ModelSim. Tools->TCL->Execute Macro and select s5_xcvr_test_tb.do.

The Quartus project is included as well. A double-click to open Quartus and another click to compile the project.

I uploaded an attachment named StratixVGX_XCVR_Test.zip but I have no idea where it ended up or how anyone would download it. Maybe that Manage Attachments button down below does both upload and download.

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Take a look at the transceiver toolkit documents I wrote here;

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html

The second shows how to use the Arria V GZ Transceivers, which are identical to those on the Stratix V (the code is the same). Go through that tutorial, and then modify it for your use. There is a simulation testbench in there.

Cheers,

Dave

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I downloaded the ZIP and PDF files and had a look at the five files in the ZIP. I see that the transceiver IP is wrapped up inside of a Qsys wrapper making it a bit more challenging to see what is going on under the hood. I was actually hoping to be able to run the testbench. In any case thanks for responding.

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I downloaded the ZIP and PDF files and had a look at the five files in the ZIP. I see that the transceiver IP is wrapped up inside of a Qsys wrapper making it a bit more challenging to see what is going on under the hood. I was actually hoping to be able to run the testbench. In any case thanks for responding.

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Altera wants you to use Qsys for transceiver designs in the latest devices. The main reason for creating the design was to be able to use the transceiver toolkit to test hardware. I'm pretty sure I put a simulation in there that should work.

I don't see your StratixVGX_XCVR_Test.zip file in your thread above.

Cheers,

Dave

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Altera wants you to use Qsys for transceiver designs in the latest devices. The main reason for creating the design was to be able to use the transceiver toolkit to test hardware. I'm pretty sure I put a simulation in there that should work.

I don't see your StratixVGX_XCVR_Test.zip file in your thread above.

Cheers,

Dave

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There are only five files inside of altera_ttk_examples_arria_v_gz.zip - assuming this is the example you are referring to. I would need all the RTL for the qsys_system module that is instantiated within ttk_example.vhd and qsys_system_tb.sv in order to run a simulation. The qsys_system_tb.do file only sets up the wave window - it does not compile the RTL or kick off vsim.

Is there another ZIP file I should be looking at?

I will upload StratixVGX_XCVR_Test.zip again. I don't know where these uploads end up...

Decided to try and send the ZIP file to you via email.

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There are only five files inside of altera_ttk_examples_arria_v_gz.zip - assuming this is the example you are referring to. I would need all the RTL for the qsys_system module that is instantiated within ttk_example.vhd and qsys_system_tb.sv in order to run a simulation. The qsys_system_tb.do file only sets up the wave window - it does not compile the RTL or kick off vsim.

Is there another ZIP file I should be looking at?

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Yeah, there is something screwy with the zip file. It has the files needed if you walk-through the document, but its missing the synthesis script that automates everything. I'll have to look at it tomorrow.

I received your zip file, I'll take a look at it tomorrow too.

Cheers,

Dave