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I downloaded the ZIP and PDF files and had a look at the five files in the ZIP. I see that the transceiver IP is wrapped up inside of a Qsys wrapper making it a bit more challenging to see what is going on under the hood. I was actually hoping to be able to run the testbench. In any case thanks for responding.
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Altera wants you to use Qsys for transceiver designs in the latest devices. The main reason for creating the design was to be able to use the transceiver toolkit to test hardware. I'm pretty sure I put a simulation in there that should work.
I don't see your StratixVGX_XCVR_Test.zip file in your thread above.
Cheers,
Dave
Honored Contributor
