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There are only five files inside of altera_ttk_examples_arria_v_gz.zip - assuming this is the example you are referring to. I would need all the RTL for the qsys_system module that is instantiated within ttk_example.vhd and qsys_system_tb.sv in order to run a simulation. The qsys_system_tb.do file only sets up the wave window - it does not compile the RTL or kick off vsim.
Is there another ZIP file I should be looking at?
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Yeah, there is something screwy with the zip file. It has the files needed if you walk-through the document, but its missing the synthesis script that automates everything. I'll have to look at it tomorrow.
I received your zip file, I'll take a look at it tomorrow too.
Cheers,
Dave
Honored Contributor
