StratixV transceiver simulation

When I say port I mean I take the old design and replace the StratixIV IP with StratixV IP leaving the architecture of the logic internal to the FPGA intact. If this was not done the design would fail to compile in Quartus since StratixIV transceivers are very different from StratixV transceivers.

The design compiles in Quartus and even functions on a real live StratixV FPGA. The only thing that does not work is the simulation model of the RX side of the transceiver.

What I will do today is to distill the project down into just the failing element by removing all the proprietary logic connected to the transceiver. That way I will have a small project that I can share.