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Altera_Forum's avatar
Altera_Forum
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10 years ago

StratixV transceiver simulation

I am simulating a simple StratixV HSSI transceiver set up in BASIC mode with 20-bit parallel data interfaces at 300 MHz. In the test bench the TX serial output is connected to the RX serial input. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I have stripped the project down into a 32M ZIP file. The only reason it is so big is because I included the Altera libraries for ModelSim that are created by the msim_setup.tcl script. I can remove these for those who already have their ModelSim environment set up with the StratixV libraries.

The simulation can be run with a few mouse clicks. I have a script which builds the IP libraries, compiles everything else, kicks off vsim and opens the Wave window.

Double-clock on the MPF to open ModelSim. Tools->TCL->Execute Macro and select s5_xcvr_test_tb.do.

The Quartus project is included as well. A double-click to open Quartus and another click to compile the project.

I uploaded an attachment named StratixVGX_XCVR_Test.zip but I have no idea where it ended up or how anyone would download it. Maybe that Manage Attachments button down below does both upload and download.