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Altera wants you to use Qsys for transceiver designs in the latest devices. The main reason for creating the design was to be able to use the transceiver toolkit to test hardware. I'm pretty sure I put a simulation in there that should work.
I don't see your StratixVGX_XCVR_Test.zip file in your thread above.
Cheers,
Dave
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There are only five files inside of altera_ttk_examples_arria_v_gz.zip - assuming this is the example you are referring to. I would need all the RTL for the qsys_system module that is instantiated within ttk_example.vhd and qsys_system_tb.sv in order to run a simulation. The qsys_system_tb.do file only sets up the wave window - it does not compile the RTL or kick off vsim.
Is there another ZIP file I should be looking at?
I will upload StratixVGX_XCVR_Test.zip again. I don't know where these uploads end up...
Decided to try and send the ZIP file to you via email.
Honored Contributor
