Source-Synch I/O Constraints

I've read just about every post by Rysc and Kaz on constraints. Many thanks for their contributions to this forum.

I'm having trouble getting the constraints right for a source synchronous interface that's driven by mux from 3 separate sources. Two of the sources are Input to Output paths, while the third source is internally generated.

Here's what I have for constraints WRT this interface so far:

create_clock -name clkA -period 37.037 
create_clock -name clkB -period 37.037 
# # Create generated clocks at output of mux
create_generated_clock -name clk_pll -source }]  -add
create_generated_clock -name clkA_muxout -source   -add
create_generated_clock -name clkB_muxout -source   -add
# # Create generated clocks at clock out pin
create_generated_clock -name clk_pll_ext -source }]  -add
create_generated_clock -name clkA_ext -source   -add
create_generated_clock -name clkB_ext -source   -add
# # Tsu of ext. device = 1.4ns
# # Th of ext. device = 1.4ns
set_output_delay -clock clk_pll_ext -min -1.4 }] -add_delay
set_output_delay -clock clk_pll_ext -max 1.4 }] -add_delay
set_output_delay -clock clkA_ext -min -1.4 }] -add_delay
set_output_delay -clock clkA_ext -max 1.4 }] -add_delay
set_output_delay -clock clkB_ext -min -1.4 }] -add_delay
set_output_delay -clock clkB_ext -max 1.4 }] -add_delay

I'm receiving the following warning from TQ:

Warning (332088): No paths exist between clock target "mclk_p" of clock "clk_pll_ext" and its clock source.  Assuming zero source clock latency.
Warning (332088): No paths exist between clock target "mclk_p" of clock "clkA_ext" and its clock source.  Assuming zero source clock latency.
Warning (332088): No paths exist between clock target "mclk_p" of clock "clkB_ext" and its clock source.  Assuming zero source clock latency.

It appears that TQ is correctly analyzing the Input to Output paths from ClkA/B to mclk. However, clk_pll to output is not being analyzed...

Here's what I have for clock groups:

set_clock_groups -asynchronous 
  .... other clocks
  -group 
set_clock_groups -exclusive 
  -group  
  -group  
  -group 

I feel like I'm missing something simple here. Any ideas?

EDIT: Just to clarify the system architecture.

The design has two synchronous input interfaces including clock and data. Those two interefaces are muxed with an internally generated set of clock and data and driven on the output. Both clock and data are muxed on the output.