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Altera_Forum
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13 years ago

Source-Synch I/O Constraints

I've read just about every post by Rysc and Kaz on constraints. Many thanks for their contributions to this forum. I'm having trouble getting the constraints right for a source synchronous int...
Altera_Forum's avatar
Altera_Forum
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13 years ago

One thing that doesn't look right to me is that you are using set_output delay three times for same node of m_data_p with reference to three clocks.

The nodes m_data_p must only be set relative to clock driving it directly.

Moreover mclk_p is not clear what it is referring to.