Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Source-Synch I/O Constraints

I've read just about every post by Rysc and Kaz on constraints. Many thanks for their contributions to this forum. I'm having trouble getting the constraints right for a source synchronous int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

kaz,

mclk_p is a muxed clock: it can be clkA, clkB or the PLL output clock.

So, the way he is constraining it looks correct to me.

kkoorndyk,

If clkA, clkB and gxb_refclk are unrelated, then you probably should cut all paths between them from analysis (ie, set them in separate clock groups) and use clock domain crossing techniques, if needed.