Source-Synch I/O Constraints

Yea, I get a bunch of warning related to the VIP cores and DDR3 but I tend to ignore those.

I don't think it's optimizing the logic away. I can see the mux in post-map technology viewer.

ClkA, ClkB and gxb_refclk are from 3 separate, unrelated ICs.

The generated clocks on the mux output are so I can cut the analysis using clock groups, otherwise I get failing paths between separate launch and latch clocks that won't actually occur because of the mux.

I tried to give just a snippet of the sdc with generic names because this design has a large number of unrelated clock domains with a lot of similar muxing.