Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Source-Synch I/O Constraints

I've read just about every post by Rysc and Kaz on constraints. Many thanks for their contributions to this forum. I'm having trouble getting the constraints right for a source synchronous int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

You're mclk_p should have the node of the mux clock as it's source, since that's what drives it. So something like:

create_generated_clock -name clkA_ext -source [get_pins {clock_mux|Equal3|combout}] -master_clock clkA_muxout [get_ports {mclk_p}] -add