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Altera_Forum
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13 years ago

Source-Synch I/O Constraints

I've read just about every post by Rysc and Kaz on constraints. Many thanks for their contributions to this forum. I'm having trouble getting the constraints right for a source synchronous int...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Sorry, that's just s snippet from my sdc file. I do have the derive_* statements in there. 

derive_pll_clocks
derive_clock_uncertainty

The input clock to the PLL is the GXB reference clock at 148.5MHz. 

create_clock -name {gxb_refclk} -period 6.734 -waveform {0.000 3.367}

Yes, I'm muxing the three clocks out on mclk_p.