Forum Discussion
New Contributorsetup timing from fifo
a strange setup timing violation:
the path is from the 'write enable' of a FIFO, to another register in the design.
it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Version) since we cant find this actual path in the design.
using the locate path command in the time quest, show me the path provided in the files below - its doesn't look like the path in violation list. also tried to understand the path with the nodes in the Data Path window but it seems a little bit confusing.
for example - locating the node `Equal0~datac` in the RTL viewer led me to a comparator, which its inputs are not the 'write enable', but 'lb_hc_rx_din' and another irrelevant input.
by the way, 'lb_hc_rx_din' is coming from the FIFO, which the 'write enable' in the violation path is its 'write enable', however I wasn't expecting it to be a problematic path since the FIFO RAM output is isolating the path (like a register).
is it possible there is a problem in the quartus, and this path should be a false path?
I am adding relevant files and screenshot. please can you help me find out what is the path and how to handle it?
regards
17 Replies
evyatarjust to be clear - even if is it possible that the path is actually starting from the RAM data output, and not the ram write enable input,
I do not find such path in my design .
sstrellSuper Contributor
Without seeing the design or the .sdc file, it's difficult to figure this out. Can you provide at least the .sdc and/or the code defining the failing path?
- RichardT_altera
Please upgrade your Quartus version to the latest version as v14.0 is quite old and the software is not downloadable anymore thus it is hard to support.
If the issue still persists, then please help to share your design so I could investigate further.
- evyatar
Hi Richard, unfortunately, upgrading the version is not possible, due to some reasons. one of them is the fact that device we use ("Cyclone V" DEVICE 5CGXFC9E6F31I7) is not supported in the newer versions.
I can add the relevant src files in personal path if it help... - sstrell
Are you saying your specific device is not supported? Because the Cyclone V family is supported in up to the latest version of Standard.
- evyatar
I will try it, however it may take some time, since I have IP Versions to upgrade, and it requires cooperation with some other colleagues.
do you have another suggestion ?
- evyatar
I managed to replicate the timing volition with version19.1.
removed all the design and simulated the attached block only.
clk preq is 125mhz
please advise
- sstrell
Can you post your .sdc?
- evyatar
actually no constrain for this specific block in the sdc beside the clock freq , only for other blocks in the original design.
attached are the SDCs for the original design.
- sstrell
You've got a very long interconnect delay going to this clock control block:
; 5.883 ; 4.766 ; RR ; IC ; 1 ; CLKCTRL_R6for both the data arrival and data required paths. Did you manually add a clock control block to your design (as an IP) or with so many clocks, was the design forced to use this clock control block to distribute the clock for the failing path? Locate the failing path to the Chip Planner to see the physical placement and to determine if there are physical resource constraints on the path which is leading to this.
