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evyatar's avatar
evyatar
Icon for New Contributor rankNew Contributor
4 years ago

setup timing from fifo

a strange setup timing violation: the path is from the 'write enable' of a FIFO, to another register in the design. it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Ver...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Without seeing the design or the .sdc file, it's difficult to figure this out. Can you provide at least the .sdc and/or the code defining the failing path?