Setup: data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk - Path #1: Setup slack is -0.586 (VIOLATED) report for ip50e_top Mon Jun 27 14:57:29 2022 Quartus II 64-Bit Version 14.1.0 Build 186 12/03/2014 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Path #1: Setup slack is -0.586 (VIOLATED) ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2014 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus II License Agreement, the Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. Path #1: Setup slack is -0.586 (VIOLATED) =============================================================================== +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Summary ; +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Property ; Value ; +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; From Node ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_fifo_wraper:\yes_lb_hc:i_lbhc_fifo_wraper|lbhc_fifo:i_lbhc_fifo|scfifo:scfifo_component|scfifo_dtg1:auto_generated|a_dpfifo_oha1:dpfifo|altsyncram_lke1:FIFOram|ram_block1a0~PORT_B_WRITE_ENABLE_REG ; ; To Node ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_rx:\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6] ; ; Launch Clock ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk ; ; Latch Clock ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk ; ; Data Arrival Time ; 15.436 ; ; Data Required Time ; 14.850 ; ; Slack ; -0.586 (VIOLATED) ; +--------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +------------------------------------------------------------------------------------+ ; Statistics ; +------------------------+--------+-------+-------------+------------+-------+-------+ ; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ; +------------------------+--------+-------+-------------+------------+-------+-------+ ; Setup Relationship ; 6.400 ; ; ; ; ; ; ; Clock Skew ; -2.024 ; ; ; ; ; ; ; Data Delay ; 4.862 ; ; ; ; ; ; ; Number of Logic Levels ; ; 4 ; ; ; ; ; ; Physical Delays ; ; ; ; ; ; ; ; Arrival Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 12 ; 6.738 ; 63 ; 0.000 ; 4.766 ; ; Cell ; ; 13 ; 3.836 ; 36 ; 0.000 ; 2.458 ; ; Data ; ; ; ; ; ; ; ; IC ; ; 5 ; 2.419 ; 49 ; 0.000 ; 1.075 ; ; Cell ; ; 6 ; 2.443 ; 50 ; 0.145 ; 0.513 ; ; uTco ; ; 1 ; 0.000 ; 0 ; 0.000 ; 0.000 ; ; Required Path ; ; ; ; ; ; ; ; Clock ; ; ; ; ; ; ; ; IC ; ; 12 ; 4.334 ; 73 ; 0.000 ; 2.452 ; ; Cell ; ; 13 ; 1.594 ; 26 ; 0.000 ; 0.472 ; +------------------------+--------+-------+-------------+------------+-------+-------+ Note: Negative delays are omitted from totals when calculating percentages +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Arrival Path ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 0.000 ; 0.000 ; ; ; ; ; launch edge time ; ; 10.574 ; 10.574 ; ; ; ; ; clock path ; ; 0.000 ; 0.000 ; ; ; ; ; source latency ; ; 0.000 ; 0.000 ; ; ; 1 ; PIN_R8 ; ii_xcvr_ref_clk ; ; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X0_Y31_N54 ; ii_xcvr_ref_clk~input|i ; ; 0.090 ; 0.090 ; RR ; CELL ; 1 ; IOIBUF_X0_Y31_N54 ; ii_xcvr_ref_clk~input|o ; ; 0.090 ; 0.000 ; RR ; IC ; 1 ; REFCLKDIVIDER_X0_Y27_N31 ; ii_xcvr_ref_clk~input~FITTER_INSERTED|refclkin ; ; 0.090 ; 0.000 ; RR ; CELL ; 12 ; REFCLKDIVIDER_X0_Y27_N31 ; ii_xcvr_ref_clk~input~FITTER_INSERTED|refclkout ; ; 0.090 ; 0.000 ; RR ; IC ; 1 ; HSSIPMACDRREFCLKSELECTMUX_X0_Y41_N37 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.pll_mux.pll_refclk_select_mux|refiqclk3 ; ; 0.090 ; 0.000 ; RR ; CELL ; 1 ; HSSIPMACDRREFCLKSELECTMUX_X0_Y41_N37 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.pll_mux.pll_refclk_select_mux|clkout ; ; 0.090 ; 0.000 ; RR ; IC ; 1 ; CHANNELPLL_X0_Y41_N32 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll|refclk ; ; 0.090 ; 0.000 ; RR ; CELL ; 2 ; CHANNELPLL_X0_Y41_N32 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll|clkcdr ; ; 0.090 ; 0.000 ; RR ; IC ; 4 ; HSSIPMATXCGB_X0_Y39_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|master_cgb.tx_cgb|clkcdrloc ; ; 0.090 ; 0.000 ; RR ; CELL ; 4 ; HSSIPMATXCGB_X0_Y39_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|master_cgb.tx_cgb|lfclkpout ; ; 0.090 ; 0.000 ; RR ; IC ; 1 ; HSSIPMATXCGB_X0_Y55_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up ; ; 0.090 ; 0.000 ; RR ; CELL ; 1 ; HSSIPMATXCGB_X0_Y55_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp ; ; 0.090 ; 0.000 ; RR ; IC ; 21 ; HSSIPMATXSER_X0_Y55_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser|lfclk ; ; 0.254 ; 0.164 ; RR ; CELL ; 1 ; HSSIPMATXSER_X0_Y55_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser|clkdivtx ; ; 0.254 ; 0.000 ; RR ; IC ; 1 ; HSSITXPCSPMAINTERFACE_X0_Y55_N60 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockinfrompma ; ; 0.254 ; 0.000 ; RR ; CELL ; 1 ; HSSITXPCSPMAINTERFACE_X0_Y55_N60 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; ; 0.254 ; 0.000 ; RR ; IC ; 2 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk ; ; 0.779 ; 0.525 ; RR ; CELL ; 1 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_top:mac10g_top_brcm_inst|xaui_alt_xcvr:xaui_alt_xcvr_inst|altera_xcvr_xaui:xaui_alt_xcvr_inst|cv_xcvr_xaui:alt_xaui_phy|av_xcvr_low_latency_phy_nr:alt_pma_0|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_tx_pcs_rbc:inst_av_hssi_8g_tx_pcs|wys~BURIED_INTCLK1 ; ; 1.117 ; 0.338 ; RR ; CELL ; 1 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|clkout ; ; 1.117 ; 0.000 ; RR ; IC ; 1 ; HSSITXPLDPCSINTERFACE_X0_Y55_N56 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|wys|clockinfrom8gpcs ; ; 1.117 ; 0.000 ; RR ; CELL ; 1 ; HSSITXPLDPCSINTERFACE_X0_Y55_N56 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|wys|pld8gtxclkout ; ; 5.883 ; 4.766 ; RR ; IC ; 1 ; CLKCTRL_R6 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0|inclk ; ; 6.144 ; 0.261 ; RR ; CELL ; 11067 ; CLKCTRL_R6 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0|outclk ; ; 8.116 ; 1.972 ; RR ; IC ; 7 ; M10K_X40_Y61_N0 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_fifo_wraper|i_lbhc_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0|clk1 ; ; 10.574 ; 2.458 ; RR ; CELL ; 40 ; M10K_X40_Y61_N0 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_fifo_wraper:\yes_lb_hc:i_lbhc_fifo_wraper|lbhc_fifo:i_lbhc_fifo|scfifo:scfifo_component|scfifo_dtg1:auto_generated|a_dpfifo_oha1:dpfifo|altsyncram_lke1:FIFOram|ram_block1a0~PORT_B_WRITE_ENABLE_REG ; ; 15.436 ; 4.862 ; ; ; ; ; data path ; ; 10.574 ; 0.000 ; ; uTco ; 40 ; M10K_X40_Y61_N0 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_fifo_wraper:\yes_lb_hc:i_lbhc_fifo_wraper|lbhc_fifo:i_lbhc_fifo|scfifo:scfifo_component|scfifo_dtg1:auto_generated|a_dpfifo_oha1:dpfifo|altsyncram_lke1:FIFOram|ram_block1a0~PORT_B_WRITE_ENABLE_REG ; ; 10.719 ; 0.145 ; RF ; CELL ; 5 ; M10K_X40_Y61_N0 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_fifo_wraper|i_lbhc_fifo|scfifo_component|auto_generated|dpfifo|FIFOram|ram_block1a0|portbdataout[35] ; ; 11.488 ; 0.769 ; FF ; IC ; 1 ; LABCELL_X45_Y61_N24 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|Equal0~1|datac ; ; 12.001 ; 0.513 ; FF ; CELL ; 3 ; LABCELL_X45_Y61_N24 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|Equal0~1|combout ; ; 12.354 ; 0.353 ; FF ; IC ; 1 ; MLABCELL_X46_Y61_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_sop_out~2|datac ; ; 12.865 ; 0.511 ; FF ; CELL ; 79 ; MLABCELL_X46_Y61_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_sop_out~2|combout ; ; 13.940 ; 1.075 ; FF ; IC ; 1 ; LABCELL_X47_Y60_N57 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]~226|datad ; ; 14.448 ; 0.508 ; FF ; CELL ; 1 ; LABCELL_X47_Y60_N57 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]~226|combout ; ; 14.670 ; 0.222 ; FF ; IC ; 1 ; LABCELL_X47_Y60_N24 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]~273|datad ; ; 15.174 ; 0.504 ; FF ; CELL ; 1 ; LABCELL_X47_Y60_N24 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]~273|combout ; ; 15.174 ; 0.000 ; FF ; IC ; 1 ; FF_X47_Y60_N26 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]|d ; ; 15.436 ; 0.262 ; FF ; CELL ; 1 ; FF_X47_Y60_N26 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_rx:\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6] ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Data Required Path ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Total ; Incr ; RF ; Type ; Fanout ; Location ; Element ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; 6.400 ; 6.400 ; ; ; ; ; latch edge time ; ; 14.950 ; 8.550 ; ; ; ; ; clock path ; ; 6.400 ; 0.000 ; ; ; ; ; source latency ; ; 6.400 ; 0.000 ; ; ; 1 ; PIN_R8 ; ii_xcvr_ref_clk ; ; 6.400 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X0_Y31_N54 ; ii_xcvr_ref_clk~input|i ; ; 6.490 ; 0.090 ; RR ; CELL ; 1 ; IOIBUF_X0_Y31_N54 ; ii_xcvr_ref_clk~input|o ; ; 6.490 ; 0.000 ; RR ; IC ; 1 ; REFCLKDIVIDER_X0_Y27_N31 ; ii_xcvr_ref_clk~input~FITTER_INSERTED|refclkin ; ; 6.490 ; 0.000 ; RR ; CELL ; 12 ; REFCLKDIVIDER_X0_Y27_N31 ; ii_xcvr_ref_clk~input~FITTER_INSERTED|refclkout ; ; 6.490 ; 0.000 ; RR ; IC ; 1 ; HSSIPMACDRREFCLKSELECTMUX_X0_Y41_N37 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.pll_mux.pll_refclk_select_mux|refiqclk3 ; ; 6.490 ; 0.000 ; RR ; CELL ; 1 ; HSSIPMACDRREFCLKSELECTMUX_X0_Y41_N37 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.pll_mux.pll_refclk_select_mux|clkout ; ; 6.490 ; 0.000 ; RR ; IC ; 1 ; CHANNELPLL_X0_Y41_N32 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll|refclk ; ; 6.490 ; 0.000 ; RR ; CELL ; 2 ; CHANNELPLL_X0_Y41_N32 ; line_network_top_i|sgmii_x2_wrap_0_inst|sgmii_alt_xcvr_x2_inst|sgmii_xcvr_2_5g_inst|A5|transceiver_core|gen.av_xcvr_native_insts[1].gen_tx_plls.gen_tx_plls.tx_plls|pll[0].pll.cmu_pll.tx_pll|clkcdr ; ; 6.490 ; 0.000 ; RR ; IC ; 4 ; HSSIPMATXCGB_X0_Y39_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|master_cgb.tx_cgb|clkcdrloc ; ; 6.490 ; 0.000 ; RR ; CELL ; 4 ; HSSIPMATXCGB_X0_Y39_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_tx_plls.gen_tx_plls.tx_plls|master_cgb.tx_cgb|lfclkpout ; ; 6.490 ; 0.000 ; RR ; IC ; 1 ; HSSIPMATXCGB_X0_Y55_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkpx6up ; ; 6.490 ; 0.000 ; RR ; CELL ; 1 ; HSSIPMATXCGB_X0_Y55_N32 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb|lfclkp ; ; 6.490 ; 0.000 ; RR ; IC ; 21 ; HSSIPMATXSER_X0_Y55_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser|lfclk ; ; 6.625 ; 0.135 ; RR ; CELL ; 1 ; HSSIPMATXSER_X0_Y55_N33 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pma|av_tx_pma|tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_pma_ser|clkdivtx ; ; 6.625 ; 0.000 ; RR ; IC ; 1 ; HSSITXPCSPMAINTERFACE_X0_Y55_N60 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockinfrompma ; ; 6.625 ; 0.000 ; RR ; CELL ; 1 ; HSSITXPCSPMAINTERFACE_X0_Y55_N60 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pcs_pma_interface|wys|clockoutto8gpcs ; ; 6.625 ; 0.000 ; RR ; IC ; 2 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk ; ; 7.097 ; 0.472 ; RR ; CELL ; 1 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_top:mac10g_top_brcm_inst|xaui_alt_xcvr:xaui_alt_xcvr_inst|altera_xcvr_xaui:xaui_alt_xcvr_inst|cv_xcvr_xaui:alt_xaui_phy|av_xcvr_low_latency_phy_nr:alt_pma_0|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch|av_hssi_8g_tx_pcs_rbc:inst_av_hssi_8g_tx_pcs|wys~BURIED_INTCLK1 ; ; 7.287 ; 0.190 ; RR ; CELL ; 1 ; HSSI8GTXPCS_X0_Y55_N58 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_8g_tx_pcs|wys|clkout ; ; 7.287 ; 0.000 ; RR ; IC ; 1 ; HSSITXPLDPCSINTERFACE_X0_Y55_N56 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|wys|clockinfrom8gpcs ; ; 7.287 ; 0.000 ; RR ; CELL ; 1 ; HSSITXPLDPCSINTERFACE_X0_Y55_N56 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|wys|pld8gtxclkout ; ; 9.739 ; 2.452 ; RR ; IC ; 1 ; CLKCTRL_R6 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0|inclk ; ; 9.974 ; 0.235 ; RR ; CELL ; 11067 ; CLKCTRL_R6 ; data_path_top_inst|nwss_10g_top_inst|mac10g_top_brcm_inst|xaui_alt_xcvr_inst|xaui_alt_xcvr_inst|alt_xaui_phy|alt_pma_0|transceiver_core|gen.av_xcvr_native_insts[0].gen_bonded_group.av_xcvr_native_inst|inst_av_pcs|ch[0].inst_av_pcs_ch|inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0|outclk ; ; 11.856 ; 1.882 ; RR ; IC ; 1 ; FF_X47_Y60_N26 ; data_path_top_inst|nwss_10g_top_inst|mac10g_adapter_top_brcm_inst|u_lb_hc|u_lb_hc_rx_wraper|\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6]|clk ; ; 12.328 ; 0.472 ; RR ; CELL ; 1 ; FF_X47_Y60_N26 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_rx:\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6] ; ; 14.950 ; 2.622 ; ; ; ; ; clock pessimism removed ; ; 14.850 ; -0.100 ; ; ; ; ; clock uncertainty ; ; 14.850 ; 0.000 ; ; uTsu ; 1 ; FF_X47_Y60_N26 ; data_path_top:data_path_top_inst|nwss_10g_top:nwss_10g_top_inst|mac10g_adapter_top:mac10g_adapter_top_brcm_inst|lb_hc:u_lb_hc|lb_hc_rx_wraper:u_lb_hc_rx_wraper|lb_hc_rx:\yes_lb_hc:i_lbhc_rx|lb_hc_rx_dout[6] ; +----------+---------+----+------+--------+--------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ---------------------------- ; Extra Fitter Information ; ---------------------------- HTML report is unavailable in plain text report export.