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evyatar
New Contributor
New Contributorsetup timing from fifo
a strange setup timing violation: the path is from the 'write enable' of a FIFO, to another register in the design. it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Ver...
evyatarNew Contributor
New ContributorI will try it, however it may take some time, since I have IP Versions to upgrade, and it requires cooperation with some other colleagues.
do you have another suggestion ?
