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evyatar
New Contributor
New Contributorsetup timing from fifo
a strange setup timing violation: the path is from the 'write enable' of a FIFO, to another register in the design. it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Ver...
evyatarNew Contributor
New Contributorjust to be clear - even if is it possible that the path is actually starting from the RAM data output, and not the ram write enable input,
I do not find such path in my design .
