Forum Discussion
evyatar
New Contributor
New Contributorsetup timing from fifo
a strange setup timing violation: the path is from the 'write enable' of a FIFO, to another register in the design. it seems like a problem in the Quartus 2 (64 bit V14.1.0 B186 12/3/14 SJ Full Ver...
evyatarNew Contributor
New Contributoractually no constrain for this specific block in the sdc beside the clock freq , only for other blocks in the original design.
attached are the SDCs for the original design.
