#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

set mii_board_delay 2
set mii_rise [expr $mii_board_delay]
set mii_fall [expr $mii_board_delay + 20.000]
set phy_min_dly [expr 2*$mii_board_delay]
set phy_max_dly [expr 15 + 2*$mii_board_delay]

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {ii_xcvr_ref_clk}            -period 6.400   -waveform { 0.000 3.200}    [get_ports { ii_xcvr_ref_clk }]
#create_clock -name {ii_sys_dbg_ref_clk}        -period 6.400   -waveform { 0.000 3.200}    [get_ports { ii_sys_dbg_ref_clk }]
create_clock -name {ii_clk_xo_25}               -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_xo_25 }]
create_clock -name {ii_clk_mxl_25}              -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_mxl_25 }]
create_clock -name {ii_clk_mxl_25_diff}         -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_mxl_25_diff }]
create_clock -name {ii_clk_1g_phy_25}           -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_1g_phy_25 }]
create_clock -name {ii_clk_1g_rgmii_25}         -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_1g_rgmii_25 }]
create_clock -name {ii_clk_10g_phy}             -period 6.206   -waveform { 0.000 3.103}    [get_ports { ii_clk_10g_phy }]
create_clock -name {ii_clk_synce_25}            -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_synce_25 }]
create_clock -name {ii_clk_brcm_spare_25[0]}    -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_brcm_spare_25[0] }]
create_clock -name {ii_clk_brcm_spare_25[1]}    -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_clk_brcm_spare_25[1] }]
create_clock -name {ii_fpga_clk10p_fb}          -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_fpga_clk10p_fb }]
create_clock -name {ii_fpga_clk11p_fb}          -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_fpga_clk11p_fb }]
create_clock -name {ii_fpga_clk2p_fb}           -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_fpga_clk2p_fb }]
create_clock -name {ii_fpga_clk0p_fb}           -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_fpga_clk0p_fb }]
create_clock -name {ii_fpga_clk10p_fb}          -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_fpga_clk10p_fb }]
create_clock -name {ii_fpga_clk1p_fb}           -period 8.000   -waveform { 0.000 4.000}    [get_ports { ii_fpga_clk1p_fb }]
create_clock -name {ii_cpu_lclk0}               -period 40.000  -waveform { 0.000 20.000}   [get_ports { ii_cpu_lclk0 }]
create_clock -name {ii_rgmii_rx_clk}            -period 8.000   -waveform {0.000  4.000}    [get_ports { ii_rgmii_rx_clk}]
create_clock -name {i_cpu_mii_clk}              -period 40.000 -waveform { 0.000 20.000 }   [get_ports {ii_tsec3_tx_clk}] 
create_clock -name {i_phy_mii_rx_clk}           -period 40.000 -waveform { 0.000 20.000 }   [get_ports {ii_fpga_mii_rx_clk}]  
#create_clock -name {i_phy_mii_tx_clk}          -period 40.000 -waveform { 0.000 20.000 }   [get_ports {ii_fpga_mii_tx_clk}] 
create_clock -name {i_phy_mii_tx_clk}           -period 40.000 -waveform { 2.000 22.000}   [get_ports {ii_fpga_mii_tx_clk }]
create_clock -name {virtual_phy_mii_tx_clk}     -period 40.000 -waveform { 0.000 20.000 } 

#**************************************************************
# Create Generated Clock
#**************************************************************

derive_pll_clocks -create_base_clocks

# Edge-Aligned RGMII TX Interface
#create_generated_clock -name oo_rgmii_tx_clk -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {oo_rgmii_tx_clk}]
# Center-Aligned RGMII TX Interface
#create_generated_clock -name oo_rgmii_tx_clk -source [get_pins {system_top_inst|clocks_inst|pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {oo_rgmii_tx_clk}]

create_generated_clock -name o_cpu_mii_rx_clk -source [get_ports {ii_tsec3_tx_clk}] -invert [get_ports {oo_cpu_tsec3_rx_clk}]

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|jat_i2c_gen[0].jat_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name jat_i2c_0_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|jat_i2c_gen[0].jat_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name jat_i2c_0_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|jat_i2c_gen[1].jat_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name jat_i2c_1_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|jat_i2c_gen[1].jat_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name jat_i2c_1_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[0].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name sfp_i2c_0_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[0].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name sfp_i2c_0_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[1].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name sfp_i2c_1_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[1].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name sfp_i2c_1_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[2].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name sfp_i2c_2_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|sfp_i2c_gen[2].sfp_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name sfp_i2c_2_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|smb_i2c_clkgen|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name clkgen_i2c_2_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|smb_i2c_clkgen|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name clkgen_i2c_2_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512

create_generated_clock [get_nets {ip20ex_bc_wrap_inst|smb_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl}] \
    -name smb_i2c_i2c_2_scl \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 1024
create_generated_clock [get_nets {ip20ex_bc_wrap_inst|smb_i2c_inst|i2c_smb_inst|u_smb_comp|U_i2c_ctrl|U_i2c_sm_ctrl|scl_mul2}] \
    -name smb_i2c_i2c_2_scl_mul2 \
    -source [get_pins {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
    -divide_by 512


###For the Mux Framer TX Clock Mux###


#**************************************************************
# Set Clock Uncertainty
#**************************************************************

derive_clock_uncertainty

#**************************************************************
# Set Input Delay
#**************************************************************

# Center-Aligned RGMII RX Interface
#Rx
set_input_delay -clock [get_clocks {ii_rgmii_rx_clk}] -max -add_delay  2.800 [get_ports {ii_rgmii_rx_ctrl ii_rgmii_rxd[*]}]
set_input_delay -clock [get_clocks {ii_rgmii_rx_clk}] -min -add_delay  1.200 [get_ports {ii_rgmii_rx_ctrl ii_rgmii_rxd[*]}]
set_input_delay -clock [get_clocks {ii_rgmii_rx_clk}] -clock_fall -max -add_delay  2.800 [get_ports {ii_rgmii_rx_ctrl ii_rgmii_rxd[*]}]
set_input_delay -clock [get_clocks {ii_rgmii_rx_clk}] -clock_fall -min -add_delay  1.200 [get_ports {ii_rgmii_rx_ctrl ii_rgmii_rxd[*]}]


# Center-Aligned input MII TX Mng Interface
set_input_delay -clock [get_clocks {i_phy_mii_rx_clk}] -max -add_delay  25 [get_ports {ii_fpga_mii_rxdv ii_fpga_mii_rxd[*]}]
set_input_delay -clock [get_clocks {i_phy_mii_rx_clk}] -min -add_delay  10 [get_ports {ii_fpga_mii_rxdv ii_fpga_mii_rxd[*]}]

# Center-Aligned input MII TX CPU Interface
set_input_delay -clock [get_clocks {i_cpu_mii_clk}] -max -add_delay  15 [get_ports {ii_tsec3_txen ii_tsec3_txd[*]}]
set_input_delay -clock [get_clocks {i_cpu_mii_clk}] -min -add_delay  1  [get_ports {ii_tsec3_txen ii_tsec3_txd[*]}]

                 
#**************************************************************
# Set Output Delay
#**************************************************************

# Edge-Aligned RGMII TX Interface
#set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -max -add_delay -0.900 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
#set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -min -add_delay -2.700 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
#set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -clock_fall -max -add_delay -0.900 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
#set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -clock_fall -min -add_delay -2.700 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]

# Center-Aligned RGMII TX Interface
set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -max -add_delay  1.000 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -min -add_delay -0.800 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -clock_fall -max -add_delay  1.000 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]
set_output_delay -clock [get_clocks {oo_rgmii_tx_clk}] -clock_fall -min -add_delay -0.800 [get_ports {oo_rgmii_tx_ctrl oo_rgmii_txd[*]}]

#mng PHY output (clock is input but data is output)
#set_output_delay -clock [get_clocks {virtual_phy_mii_tx_clk}] -max -add_delay $phy_max_dly  [get_ports {oo_fpga_mii_txen oo_fpga_mii_txd[*]}]
#set_output_delay -clock [get_clocks {virtual_phy_mii_tx_clk}] -min -add_delay $phy_min_dly  [get_ports {oo_fpga_mii_txen oo_fpga_mii_txd[*]}]

#CPU mii output (clock is iverted from input clock)
set_output_delay -clock [get_clocks {o_cpu_mii_rx_clk}] -max -add_delay  10  [get_ports {oo_cpu_tsec3_crs_dv oo_cpu_tsec3_rxd[*]}]
set_output_delay -clock [get_clocks {o_cpu_mii_rx_clk}] -min -add_delay -10  [get_ports {oo_cpu_tsec3_crs_dv oo_cpu_tsec3_rxd[*]}]


#**************************************************************
# Set False Path
#**************************************************************

# Edge-Aligned RGMII TX Interface
set_false_path -fall_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {oo_rgmii_tx_clk}] -setup
set_false_path -rise_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {oo_rgmii_tx_clk}] -setup
set_false_path -fall_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {oo_rgmii_tx_clk}] -hold
set_false_path -rise_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {oo_rgmii_tx_clk}] -hold

# Add by Aviv Yaacobi (TRNG) - 05/09/2021:
set_false_path -from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_v2_i|pll_xo_25m_v2_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] -to [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_xo_25m_inst|pll_xo_25m_inst|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]

#**************************************************************
# Set Multicycle Path
#**************************************************************

# Edge-Aligned RGMII TX Interface
set_multicycle_path 1 -setup -end -rise_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {oo_rgmii_tx_clk}]
set_multicycle_path 1 -setup -end -fall_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {oo_rgmii_tx_clk}]
set_multicycle_path 0 -hold  -end -rise_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {oo_rgmii_tx_clk}]
set_multicycle_path 0 -hold  -end -fall_from [get_clocks {system_top_inst|clocks_inst|\pnr_switch:pll_rgmii_rx_125m_inst|pll_rgmii_rx_125m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {oo_rgmii_tx_clk}]

#**************************************************************
# Set Maximum Delay
#**************************************************************

#**************************************************************
# Set Minimum Delay
#**************************************************************

#**************************************************************
# Set Input Transition
#**************************************************************