setup timing from fifo

You've got a very long interconnect delay going to this clock control block:

;   5.883  ;   4.766 ; RR ; IC   ; 1      ; CLKCTRL_R6 

for both the data arrival and data required paths. Did you manually add a clock control block to your design (as an IP) or with so many clocks, was the design forced to use this clock control block to distribute the clock for the failing path? Locate the failing path to the Chip Planner to see the physical placement and to determine if there are physical resource constraints on the path which is leading to this.