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JOter's avatar
JOter
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6 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift.

The design is working but we have detected that "set_output_delay" dosen't apply. For example, we have compared, in an oscilloscope, the delay beetwen the signals CLK and a bit ADD[15] bus and it is constant for any "set_out_delay".

We are using the next constrains configuration:

create_clock -name RAM_CLK -period 16 [get_ports {RAM_CLK}]

create_generated_clock -name vt_RAM_CLK -source [get_ports {RAM_CLK}] -divide_by 1 -multiply_by 1 -phase 180

set_output_delay -clock {vt_RAM_CLK} 3 [get_ports {RAM_ADD[15] }].

In next figure, you can see timing of both signals.

The delay is contant for any "output_delay" value (0, 1, 2, 3..).

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  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I understand that the delay is the same. Does the delay exceed the delay set in the sdc? The result in the timing analysis is the worst case scenario. Just would like to make sure that the delay measured is within the range.

    Thanks.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    The phisical delay lower to the max/min delay setting.

    Regards

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    In the real design, we use a phase 190º shift clock and is it working. For the test, we are using a 0º phase shift clock, and is also working even without any constraints.

    Anyway, it is strange for me, the timing in the oscilloscope of both signals (data and clock) are the same for any "output_delay value" (form o to 12n for example). In some of them Time quest reports setup error.

    Regards

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    Our design is different to figure 10 architecture. We generate the CLOCK in a FPGA PLL. You can see more details in my first message. The FPGA and the memory are very near, and I have connected both probes near memory pins.

    For example, the inpout delay setting ir working properly. The design includes 16 LVDS DDR channels and 4GHz, and if I modify the setting to a wrong value we get wrong data.

    Regards

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    I want to say values out of range of Inputs requirements.

    Regards

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    It is expected for the receiver end to receive the wrong data if the value set is out of the range of the input requirement.You have to make sure that the value set is with the input requirement of the receiver end.

    Please let me know if I understand wrongly. There is no timing violation reported in the Timing Analysis and the signal is being captured correctly at the reciever end when the delay is set within the range of input requirement.

    Thanks.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    It seems I have not explain correctly.

    In the input case, the setting is defined correctly the setting, but I modified it to a wrong value to confirm that the constraints apply as it was expected.

    In reference to the output setting, it is also working properly but I want to test that I'am able to modified the CLK-signal timing using a wide range of max/min (from 0 to 12 for example) "output_delay". But the real delay is the same.

    Regards