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JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
7 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

It is expected for the receiver end to receive the wrong data if the value set is out of the range of the input requirement.You have to make sure that the value set is with the input requirement of the receiver end.

Please let me know if I understand wrongly. There is no timing violation reported in the Timing Analysis and the signal is being captured correctly at the reciever end when the delay is set within the range of input requirement.

Thanks.