Forum Discussion
JOter
New Contributor
New ContributorSet_output_delay commands does not apply to the output signal
We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
I understand that the delay is the same. Does the delay exceed the delay set in the sdc? The result in the timing analysis is the worst case scenario. Just would like to make sure that the delay measured is within the range.
Thanks.
