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JOter's avatar
JOter
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6 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

In the real design, we use a phase 190º shift clock and is it working. For the test, we are using a 0º phase shift clock, and is also working even without any constraints.

Anyway, it is strange for me, the timing in the oscilloscope of both signals (data and clock) are the same for any "output_delay value" (form o to 12n for example). In some of them Time quest reports setup error.

Regards