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JOter's avatar
JOter
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6 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Our design is different to figure 10 architecture. We generate the CLOCK in a FPGA PLL. You can see more details in my first message. The FPGA and the memory are very near, and I have connected both probes near memory pins.

For example, the inpout delay setting ir working properly. The design includes 16 LVDS DDR channels and 4GHz, and if I modify the setting to a wrong value we get wrong data.

Regards