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JOter's avatar
JOter
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6 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

It seems I have not explain correctly.

In the input case, the setting is defined correctly the setting, but I modified it to a wrong value to confirm that the constraints apply as it was expected.

In reference to the output setting, it is also working properly but I want to test that I'am able to modified the CLK-signal timing using a wide range of max/min (from 0 to 12 for example) "output_delay". But the real delay is the same.

Regards