Forum Discussion
JOter
New Contributor
New ContributorSet_output_delay commands does not apply to the output signal
We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
Where do you probe the signal?
Referring to Figure 10 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf, do you probe at the data_out of the FPGA or data_in of the external device?
Thanks.
