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Altera_Forum's avatar
Altera_Forum
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9 years ago

SDC constraints: One GCLK with two net names.

I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment.

I would like a simple way to set_false_path between the two uses of this one clock, rather than having many set_false_path constraints for all the logic that is clocked by the two clocks.

Is it possible to define two clocks in the SDC by source code net name, rather than the actual clock source?

I can work around the issue by using a PLL to generate the second clock from the first at the same frequency, but that is expensive in resource and power for doing nothing.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Currently no, they are treated as one big clock domain and there is no easy way to differentiate between them. I think this may change in the future, but not positive.

    (I assume in most cases they just drive different hierarchies, and only in a few places might they interact, but that's just an assumption.)

    Also note that you can treat them as one clock domain and false path the simple ones you know about. If your design meets timing, then who cares if you missed some. If it fails timing in places that are unrelated to these transfers, it's probably fine. In fact, maybe start the design with two separate clock domains that are cut from each other but use more power. Work on it and eventually close timing. Then merge them onto one clock domain and see if it suddenly fails timing(in which case you have to add FPs to fix it), but most likely it will work.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Actually, they interact in many places. One domain is a bus accessing a lot of control registers. The registers control the behavior of an image data pipe that happens to use the same clock. A change to a register changes how the pipe manipulates the data flowing through, but it doesn't matter at all on which clock it starts doing that. So there are a zillion timing problems if I don't define the false paths.

    The original clock is the core clock output from a pcie interface. The register space is accessed over pcie, but I also DMA image data in and out through pcie, so it is convenient to use the same clock for both domains. The only point where their relative timing matters is within the pcie block.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Sorry for being off topic but I am a bit curious, one clock source leads to two unrelated clock domains? is that because of some phase issues or delay from source that can't be handled by fitter.?

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Yes. As explained in my last post, the PCIe interface is used for two distinct functions. First, to access control registers, and second to transfer image data. From the PCIe perspective, these are completely independent. But in the image pipe, control register outputs directly are inputs to image pipe logic. The timing of those inputs doesn't matter at all, but the fitter assumes it does, and is unable to close timing in all the many spots. So a false paths constraint relieves all that effort.

    Of course, I could actually use separate clocks for the register and image pipe domains, by adding clock crossing FIFOs to the image pipe. It's just added resources for no real need. It is so simple to have everything on the same clock.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Check out the get_fanout SDC extension collection (not standard SDC). You can use this to differentiate when the clock is used for one purpose or another and false path only the collection you want. Best example of its use is if a signal is used as a clock enable on some registers and a divide-by-two clock on other registers. You can separate these uses for the same signal with get_fanout and false path appropriately.