SDC constraints: One GCLK with two net names.

Yes. As explained in my last post, the PCIe interface is used for two distinct functions. First, to access control registers, and second to transfer image data. From the PCIe perspective, these are completely independent. But in the image pipe, control register outputs directly are inputs to image pipe logic. The timing of those inputs doesn't matter at all, but the fitter assumes it does, and is unable to close timing in all the many spots. So a false paths constraint relieves all that effort.

Of course, I could actually use separate clocks for the register and image pipe domains, by adding clock crossing FIFOs to the image pipe. It's just added resources for no real need. It is so simple to have everything on the same clock.