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Altera_Forum
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9 years ago

SDC constraints: One GCLK with two net names.

I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment. I would like a simple w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Check out the get_fanout SDC extension collection (not standard SDC). You can use this to differentiate when the clock is used for one purpose or another and false path only the collection you want. Best example of its use is if a signal is used as a clock enable on some registers and a divide-by-two clock on other registers. You can separate these uses for the same signal with get_fanout and false path appropriately.