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Honored Contributor
Honored ContributorSDC constraints: One GCLK with two net names.
I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment. I would like a simple w...
Altera_ForumHonored Contributor
Honored ContributorActually, they interact in many places. One domain is a bus accessing a lot of control registers. The registers control the behavior of an image data pipe that happens to use the same clock. A change to a register changes how the pipe manipulates the data flowing through, but it doesn't matter at all on which clock it starts doing that. So there are a zillion timing problems if I don't define the false paths.
The original clock is the core clock output from a pcie interface. The register space is accessed over pcie, but I also DMA image data in and out through pcie, so it is convenient to use the same clock for both domains. The only point where their relative timing matters is within the pcie block.
