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Honored Contributor
Honored ContributorSDC constraints: One GCLK with two net names.
I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment. I would like a simple w...
Altera_ForumHonored Contributor
Honored ContributorSorry for being off topic but I am a bit curious, one clock source leads to two unrelated clock domains? is that because of some phase issues or delay from source that can't be handled by fitter.?
