Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

SDC constraints: One GCLK with two net names.

I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment. I would like a simple w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Sorry for being off topic but I am a bit curious, one clock source leads to two unrelated clock domains? is that because of some phase issues or delay from source that can't be handled by fitter.?