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Altera_Forum
Honored Contributor
Honored ContributorSDC constraints: One GCLK with two net names.
I have a large design with one GCLK that is used as two unrelated clocks. The clocks have two names in the Verilog source, but refer to the same GCLK net, by assignment. I would like a simple w...
Altera_ForumHonored Contributor
Honored ContributorCurrently no, they are treated as one big clock domain and there is no easy way to differentiate between them. I think this may change in the future, but not positive.
(I assume in most cases they just drive different hierarchies, and only in a few places might they interact, but that's just an assumption.) Also note that you can treat them as one clock domain and false path the simple ones you know about. If your design meets timing, then who cares if you missed some. If it fails timing in places that are unrelated to these transfers, it's probably fine. In fact, maybe start the design with two separate clock domains that are cut from each other but use more power. Work on it and eventually close timing. Then merge them onto one clock domain and see if it suddenly fails timing(in which case you have to add FPs to fix it), but most likely it will work.
