Schematic Symbol Parameter in Hex

This does not work. here is some test code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test2 is
	generic (
		addr : natural := 16#4000#
	);
	port (
		i_clk : in std_logic;
		o	   : out std_logic_vector(15 downto 0)
	);
end;

architecture arch of test2 is
	signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16));
begin
	o <= reg;
end;

generating a symbol from this code results in the following table:

Parameter | Value | Type
addr      | 16384 | Signed Integer

and synthesizes correctly to

using

Parameter  | Value | Type
addr       | 4000  | Hexadecimal

results in an error:

Error (10515): VHDL type mismatch error at /asd.vhd(8): natural type does not match string literal

using

Parameter | Value | Type
addr      | 4000  | Auto

synthesizes incorrectly to:

The one you get by clickling File -> Create/Update -> Create Symbole Files from Current File in the*.vhd file.

the upper block with with Verilog works, VHDL does not.