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pertrl's avatar
pertrl
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Schematic Symbol Parameter in Hex

Hello, how can I input a hexadecimal value in the parameter table of a block diagram/schematic file (.bdf)? behind the block is the following VHDL code: entity reg is generic ( constant REG_B...
Hdl
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    Done testing. Use the following for example:

    addr : std_logic_vector(15 downto 0) := x"FFFF"


    Then change line 16 from:

    signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16));

    to:

    signal reg : std_logic_vector(15 downto 0) := addr;


    You'll be able to use Hexadecimal type for example value AAAA


    Thanks,

    Best Regards,

    Sheng


FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
the problem doesn't seem related to VHDL support in my view. You can neither send a hexadecimal literal to a numerical Verilog module parameter. Only decimal numbers seem to be accepted as block parameters for numerical values.