Forum Discussion
Schematic Symbol Parameter in Hex
- 2 years ago
Hi,
Done testing. Use the following for example:
addr : std_logic_vector(15 downto 0) := x"FFFF"
Then change line 16 from:
signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16));
to:
signal reg : std_logic_vector(15 downto 0) := addr;
You'll be able to use Hexadecimal type for example value AAAA
Thanks,
Best Regards,
Sheng
Hi,
To input a hexadecimal value in the parameter table of a block diagram/schematic file (.bdf), set the (Type) to either Auto or Hexadecimal then under (Value) straight away give a value for example like: a, not need the symbol x""
Thanks,
Regards,
Sheng
- pertrl2 years ago
New Contributor
This does not work. here is some test code:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test2 is generic ( addr : natural := 16#4000# ); port ( i_clk : in std_logic; o : out std_logic_vector(15 downto 0) ); end; architecture arch of test2 is signal reg : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(addr, 16)); begin o <= reg; end;generating a symbol from this code results in the following table:
Parameter | Value | Type addr | 16384 | Signed Integerand synthesizes correctly to
using
Parameter | Value | Type addr | 4000 | Hexadecimalresults in an error:
Error (10515): VHDL type mismatch error at /asd.vhd(8): natural type does not match string literal
using
Parameter | Value | Type addr | 4000 | Autosynthesizes incorrectly to: