RTL Viewer

If I make two separte files I can achieve the desired. but I want to have only one file.

@nic_@ yes, here you can understand about you adders and comparators, and register structure too.

The early you undesrstand what you can get the early you achive the desired structure.

If you experienced user in FPGA you tend to write program as template. Yoo should do like "this" to achive "this".

Analysis and Elaboration - iterative process until you get someone that meet you. After that you can do fitting, optimisation, synthesis.

So to reduce number of Analysis and Elaboration steps just make as many architecture as you can than look at the result and choose what is suitable for you.

architecture is selected when you instantiate the entity. If you do it via a component you need to use a configuration to select the appropriate architecture

component my_comp is ....
for all: my_comp
  use entity work.my_ent(arch_sel);

Or better, use direct instantiation:

inst1 : entity work.my_ent(arch_sel);

If you have two architectures at the top level, apart from asking why, I dont actually know how Quartus behaves. Multiple architures, when used, are only usually used for differentiating a simulation model of an entity verses a RTL implementation. I have never used multiple architectures and it is highly discouraged in industry. If you want different behaviours then create different entities (or use generics to control behaviour).

I do not what different entities at design.

@Tricky, you are right - use configurtion but do it as late as possible. How you can control structure through "generic" you will should used "generate" after all? it is better to write procedure/fucntion. but it is another level of programming.

Okay. How many architecture you could provide for full-adder for 3 32-bit words or for 6 64-bit words? How you can compare it in one step in design cycle/what about simulation. WE stop here and say for ownself "there a lot of ready-made code. why not just using it". I answer for myself "let's modify that code to meet my project requirments".

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I do not what different entities at design.

@Tricky, you are right - use configurtion but do it as late as possible. How you can control structure through "generic" you will should used "generate" after all? it is better to write procedure/fucntion. but it is another level of programming.

Okay. How many architecture you could provide for full-adder for 3 32-bit words or for 6 64-bit words? How you can compare it in one step in design cycle/what about simulation. WE stop here and say for ownself "there a lot of ready-made code. why not just using it". I answer for myself "let's modify that code to meet my project requirments".

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Just instantiate two adders instead of two architectures and assign to two outputs. In practice I never need to do more than one architecture. Universities love it.

So. What does style depend on?

@kaz, your advice good, add it to @Tricky and we get "make as many architecture you want, then make new entity where all desired architecture instained through configuration or direct instance. Enjoy". I 'll get one file with all desired architecture that wlll be a parallel structure .

Open any Viewer (RTL,Topology) and "enjoy" (sarcasm). Is it convenienced for me?

It 's better to add in quartus ability to choose which architecture(s) to open. I don't like the way that exist for today.

@Tricky, you understand . only one architecture but which one, it seems it uses one that latter in the file.

to get the second you should use another entity where you instained two componets. Is it convenienced?

Research/design cycle becomes longer at this stage - to get rightfully adjusted vhdl code. As alternative - we all together pointed it out in the thread.

We should think of "when your experienced you don't bother with such question 'how to' cause you know time-prooven designs"

Look up how to write configurations. You can put them in a separate file to control which entities use which architecture.

I suggest you stop using separate architectures. Your other posts also suggest you are trying to write code against convention.

If you want to raise issue with the way the tools work, you need to be raising the issue direct with altera.

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Look up how to write configurations. You can put them in a separate file to control which entities use which architecture.

I suggest you stop using separate architectures. Your other posts also suggest you are trying to write code against convention.

If you want to raise issue with the way the tools work, you need to be raising the issue direct with altera.

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1 line. it is acceptable

2 line. I can stop use separate architecture , but if I find any mistake in design i should go step-by-step to remove one.

convention could help reduce mistakes. but fully-qualified condition in if-statement and nested-if that cover the same input set produce different results. even more you can get a lot of multiplexors instead of good scheme. thats belong to "how to write code right".

3 line. raising ticket. "Improve your software. Give me more VHDL support". I understand why only one architecture . look at verilog , schematic... but it is not true for vhdl. I think for now software cut off power of VHDL.