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Look up how to write configurations. You can put them in a separate file to control which entities use which architecture.
I suggest you stop using separate architectures. Your other posts also suggest you are trying to write code against convention.
If you want to raise issue with the way the tools work, you need to be raising the issue direct with altera.
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1 line. it is acceptable
2 line. I can stop use separate architecture , but if I find any mistake in design i should go step-by-step to remove one.
convention could help reduce mistakes. but fully-qualified condition in if-statement and nested-if that cover the same input set produce different results. even more you can get a lot of multiplexors instead of good scheme. thats belong to "how to write code right".
3 line. raising ticket. "Improve your software. Give me more VHDL support". I understand why only one architecture . look at verilog , schematic... but it is not true for vhdl. I think for now software cut off power of VHDL.
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