QSYS Subsystem Export Port order

So I assume there it is simply not intended to be possible by Altera, is that correct?

No unfortunately both variants do not work:

• Component Instantiation Tab is empty for .qsys submodules.
• The Interface Requirements tab shows even a different Port order than what is in the XML .qsys file or to what is the order in the GUI in the top level.

I know this works for individual components, but try selecting the added subsystem and then go to the Component Instantiation tab.  Can you click and drag the interfaces on the Signals and Interfaces tab?

If not there, try opening the subsystem .qsys and then looking at the Interface Requirements tab.  The left side of that tab shows the interfaces of the current system and I forget if you can drag and reorder them there.

The Interface looks like this currently:

I expected the Ports to have the same order as in the .qsys XML file:

<altera:altera_interface_boundary>
  <altera:interface_mapping altera:name="clk322m_in" altera:internal="clk322m_bridge.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_90m_in" altera:internal="clk_90m.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_pcie_in" altera:internal="clk_pcie.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset" altera:internal="reset_bridge_0.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset_pcie" altera:internal="reset_pcie.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="mm_bridge_0_m0" altera:internal="mm_bridge_0.m0" altera:type="avalon" altera:dir="start"></altera:interface_mapping>
</altera:altera_interface_boundary>

As for the reason, why I would like to define the order or exported Ports:

• If using multiple QSYS files in a hierarchy, it can get very confusing and difficult to read if the interface ports of submodules appear unordered. 
• Especially for submodules with different clock domains and/or multiple Avalon Ports it would be extremely beneficial from a documentation & readability point of view to be able to arrange the Ports in a meaningful way.

In fact this has been possible in other versions of Quartus. I can definitely state, that it has worked flawless with Quartus 21.1 Standard.

best regards

Fabian

Could you share a screenshot showing your expected result and the actual result?
Is there any specific IP in the subsystem for which you want to change the order of the exported ports?
For better understanding, could you also explain why you would like to define the order of the exported ports in a Platform Designer subsystem?

Regards,
Richard Tan

Concerning 2. the modified section in the .qsys XML file is looking like this:

<altera:altera_interface_boundary>
  <altera:interface_mapping altera:name="clk322m_in" altera:internal="clk322m_bridge.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_90m_in" altera:internal="clk_90m.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_pcie_in" altera:internal="clk_pcie.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset" altera:internal="reset_bridge_0.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset_pcie" altera:internal="reset_pcie.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="mm_bridge_0_m0" altera:internal="mm_bridge_0.m0" altera:type="avalon" altera:dir="start"></altera:interface_mapping>
</altera:altera_interface_boundary>