QSYS Subsystem Export Port order

Concerning 2. the modified section in the .qsys XML file is looking like this:

<altera:altera_interface_boundary>
  <altera:interface_mapping altera:name="clk322m_in" altera:internal="clk322m_bridge.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_90m_in" altera:internal="clk_90m.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_pcie_in" altera:internal="clk_pcie.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset" altera:internal="reset_bridge_0.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset_pcie" altera:internal="reset_pcie.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="mm_bridge_0_m0" altera:internal="mm_bridge_0.m0" altera:type="avalon" altera:dir="start"></altera:interface_mapping>
</altera:altera_interface_boundary>