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FabianL
Occasional Contributor
Occasional ContributorQSYS Subsystem Export Port order
Hello, I'm having a hierarchical QSYS System which uses other QSYS file as subsystem. My problem is, that I cannot find a way to reliable define the order of export Ports of the subsystem, i.e. t...
FabianLOccasional Contributor
Occasional ContributorConcerning 2. the modified section in the .qsys XML file is looking like this:
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="clk322m_in" altera:internal="clk322m_bridge.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
<altera:interface_mapping altera:name="clk_90m_in" altera:internal="clk_90m.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
<altera:interface_mapping altera:name="clk_pcie_in" altera:internal="clk_pcie.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="reset_bridge_0.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
<altera:interface_mapping altera:name="reset_pcie" altera:internal="reset_pcie.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
<altera:interface_mapping altera:name="mm_bridge_0_m0" altera:internal="mm_bridge_0.m0" altera:type="avalon" altera:dir="start"></altera:interface_mapping>
</altera:altera_interface_boundary>
