Altera_Forum
Honored Contributor
12 years agoOrdering of Ports for exported Qsys signal conduits
Hi,
I have a design with a Qsys that is slowley growing. I find that each time I export another signal conduit it gets added to the bottom of the component. This is the same for the generated VHDL component, or for the block symbol. I'd really like to keep the exported signals together in a logical order, rather than just in the order they happened to be exported. For example all the external memory interfaces to be kept together. I'm currently using a schematic top level for my design with the Qsys system connected to a number of other symbols representing VHDL components. Currently I can only think of two solutions: 1) Edit the auto generated .bsf file every time I add or remove a conduit. 2) Delete all the exported conduits from my Qys design, and then go round exporting them in the order I want them to appear. Neither of these are ideal, I'd be interested to hear if anybody has any better solutions, this must start to become an issue in many designs. Mark