Compilation error due to LPDDR5 I/O standard setting

I don't use Altera LPDDR5 IP in Agilex 5 E-series device, just write a Multi-Purpose Command to access the LPDDR5 device. And in the Quartus Pin planner, set the related pins for 0.7V LVSTL and DIFFERENTIAL 0.7-V LVSTL, I found that it would cause the fitter error. It seems that 0.7V LVSTL and DIFFERENTIAL 0.7-V LVSTL only can support Altera LPDDR5 IP usage.

Error message as below,

Error(24116): I/O standard option is set to Differential 0.7-V LVSTL for pin lp5a_ck_t~output but the GPIO usage mode does not support the setting.  

But if I try to modify I/O standard to 1.05V LVSTL and DIFFERENTIAL 1.05-V LVSTL for all related pins, and it can get the compilation pass.

Could you help to provide workaround for this issue?