QSYS Subsystem Export Port order

The Interface looks like this currently:

I expected the Ports to have the same order as in the .qsys XML file:

<altera:altera_interface_boundary>
  <altera:interface_mapping altera:name="clk322m_in" altera:internal="clk322m_bridge.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_90m_in" altera:internal="clk_90m.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="clk_pcie_in" altera:internal="clk_pcie.in_clk" altera:type="clock" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset" altera:internal="reset_bridge_0.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="reset_pcie" altera:internal="reset_pcie.in_reset" altera:type="reset" altera:dir="end"></altera:interface_mapping>
  <altera:interface_mapping altera:name="mm_bridge_0_m0" altera:internal="mm_bridge_0.m0" altera:type="avalon" altera:dir="start"></altera:interface_mapping>
</altera:altera_interface_boundary>

As for the reason, why I would like to define the order or exported Ports:

• If using multiple QSYS files in a hierarchy, it can get very confusing and difficult to read if the interface ports of submodules appear unordered. 
• Especially for submodules with different clock domains and/or multiple Avalon Ports it would be extremely beneficial from a documentation & readability point of view to be able to arrange the Ports in a meaningful way.

In fact this has been possible in other versions of Quartus. I can definitely state, that it has worked flawless with Quartus 21.1 Standard.

best regards

Fabian