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CPope's avatar
CPope
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7 years ago

QSYS HDL generation error. What is the cause?

I am experiencing a QSYS HDL generation error for my QSYS design. I have tried running an Altera_Lite platform for Quartus version 15.1, 16.0 and 16.1 tools and the same thing happens for each different installation. Below is a portion of the report during a QSYS generation. It fails the generation of the Timer RTL or something.

Any help is most appreciated.

Info: onchip_flash_0: Generating top-level entity altera_onchip_flash

Info: onchip_flash_0: "Embedded_1" instantiated altera_onchip_flash "onchip_flash_0"

Info: onchip_memory2_0: Starting RTL generation for module 'Embedded_1_onchip_memory2_0'

Info: onchip_memory2_0: Generation command is [exec C:/altera_lite/16.0/quartus/bin64/perl/bin/perl.exe -I C:/altera_lite/16.0/quartus/bin64/perl/lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin/europa -I C:/altera_lite/16.0/quartus/sopc_builder/bin/perl_lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Embedded_1_onchip_memory2_0 {--dir=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0006_onchip_memory2_0_gen/} --quartus_dir=C:/altera_lite/16.0/quartus --verilog {--config=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0006_onchip_memory2_0_gen//Embedded_1_onchip_memory2_0_component_configuration.pl} --do_build_sim=0 ]

Info: onchip_memory2_0: Done RTL generation for module 'Embedded_1_onchip_memory2_0'

Info: onchip_memory2_0: "Embedded_1" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"

Info: spi_0: Starting RTL generation for module 'Embedded_1_spi_0'

Info: spi_0: Generation command is [exec C:/altera_lite/16.0/quartus/bin64/perl/bin/perl.exe -I C:/altera_lite/16.0/quartus/bin64/perl/lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin/europa -I C:/altera_lite/16.0/quartus/sopc_builder/bin/perl_lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi -- C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_spi/generate_rtl.pl --name=Embedded_1_spi_0 {--dir=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0007_spi_0_gen/} --quartus_dir=C:/altera_lite/16.0/quartus --verilog {--config=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0007_spi_0_gen//Embedded_1_spi_0_component_configuration.pl} --do_build_sim=0 ]

Info: spi_0: Done RTL generation for module 'Embedded_1_spi_0'

Info: spi_0: "Embedded_1" instantiated altera_avalon_spi "spi_0"

Info: sysid_qsys_0: "Embedded_1" instantiated altera_avalon_sysid_qsys "sysid_qsys_0"

Info: timer_0: Starting RTL generation for module 'Embedded_1_timer_0'

Info: timer_0: Generation command is [exec C:/altera_lite/16.0/quartus/bin64//perl/bin/perl.exe -I C:/altera_lite/16.0/quartus/bin64//perl/lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin/europa -I C:/altera_lite/16.0/quartus/sopc_builder/bin/perl_lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Embedded_1_timer_0 {--dir=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0009_timer_0_gen/} --quartus_dir=C:/altera_lite/16.0/quartus --verilog {--config=C:/Users/Charles Pope/AppData/Local/Temp/alt7886_796220697038017651.dir/0009_timer_0_gen//Embedded_1_timer_0_component_configuration.pl} --do_build_sim=0 ]

Info: timer_0:

Info: timer_0: ERROR:

Info: timer_0: Failure reading 'C:/Users/Charles' -

Error: timer_0: Failed to generate module Embedded_1_timer_0

Info: timer_0: Done RTL generation for module 'Embedded_1_timer_0'

Info: timer_0: "Embedded_1" instantiated altera_avalon_timer "timer_0"

Error: Generation stopped, 7 or more modules remaining

Info: Embedded_1: Done "Embedded_1" with 15 modules, 15 files

Error: qsys-generate failed with exit code 1: 2 Errors, 6 Warnings

Info: Finished: Create HDL design files for synthesis

4 Replies

  • JOHI's avatar
    JOHI
    Icon for Contributor rankContributor
    7 years ago

    Hello CPope,

    There is 1 message that could be of use in your list:

    Info: timer_0: Failure reading 'C:/Users/Charles' -

    This could indicate that there is someting wrong with your configuration, some reference is broken or something else.

    What you could do is backup your configuration and delete ip block by ip block until the design compiles.

    Best Regards,

    Johi

  • CPope's avatar
    CPope
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi Johi,

    Thank you very much for your quick response.

    I took your advice and I did a fresh install of the Altera_lite v16.0 tools (after uninstalling the Altera tools on my Windows10 computer of course)

    After that install I rebuilt my design on a separate drive. Hopefully you can see the screenshot of my Qsys system below with everything connected.

    When I compile this I get the same error as before to do with the Timer.

    I have captured the executeable line to provide more specifics below:Info: timer_0:

    Generation command is [exec C:/altera_lite/16.0/quartus/bin64//perl/bin/perl.exe -I C:/altera_lite/16.0/quartus/bin64//perl/lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin/europa -I C:/altera_lite/16.0/quartus/sopc_builder/bin/perl_lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=embedded_1_timer_0 {--dir=C:/Users/Charles Pope/AppData/Local/Temp/alt7889_5304015320983038483.dir/0154_timer_0_gen/} --quartus_dir=C:/altera_lite/16.0/quartus --verilog {--config=C:/Users/Charles Pope/AppData/Local/Temp/alt7889_5304015320983038483.dir/0154_timer_0_gen//embedded_1_timer_0_component_configuration.pl} --do_build_sim=0 ]

    So I then did as you suggested..... by unchecking the TIMER_0 in the Qsys design and then I reran the QSYS build and everything worked!!!!

    So there is clearly something wrong with the timer path I believe. All of the othe components in the altera_lite/16.0.... are found and located and included in the QSYS build.

    Below is the altera_lite install library for the sopc_builder_ip:

    Any ideas?

    Charles

  • JOHI's avatar
    JOHI
    Icon for Contributor rankContributor
    7 years ago

    Hello Charles,

    I am happy you are one step forward.

    What you could try is really remove the timer from your qsys design, recompile, delete the output directory, add it, and recompile again.

    The moment you add & compile a component, a copy is made from Intel supplied IP (tcl, vhdl, verilog) to directories of your project directory.

    If something is went wrong with this copy process remove & add redoes the step that could have gone wrong.

    If you uncheck the component I do not know if the same happens behind the back door.

    Other solution: make backup of your project (quartus/project/archive project) and trow it on the forum...

    (Not making any promises.)

    Best Regards,

    Johi.

    • CPope's avatar
      CPope
      Icon for New Contributor rankNew Contributor
      7 years ago

      Hi Johi,

      Well I am finally getting back to this particular FPGA project.

      After discovering in my QSYS design that the Timer block was not getting generated (but the other 15 or so QSYS blocks generated OK) I decided to try a fresh, new QSYS design that just has the Clock Source IP and the Timer IP blocks. The clock and reset are hooked up to the Timer and the other Timer ports are exported (see attached). The error report is also attached. The qsys folder and sub-folder directory contents are also attached.

      The Timer block works OK with Qsys on my computer at work but for BOTH of my computers at home the same QSYS failure occurs. The computer at work has a Standard Quartus Pro install (v15.1) but the computers at home have the Quartus Pro Lite v15.1.

      I have also tried copying the Timer IP (sopc_builder_ip/altera_avalon_timer) from the computer at work into the altera install directory on my home computers.

      This is mysterious since all of the other QSYS IP blocks get generated with no problems.

      Any other ideas on what to check?

      Charles