New Contributor
ContributorHello Charles,
I am happy you are one step forward.
What you could try is really remove the timer from your qsys design, recompile, delete the output directory, add it, and recompile again.
The moment you add & compile a component, a copy is made from Intel supplied IP (tcl, vhdl, verilog) to directories of your project directory.
If something is went wrong with this copy process remove & add redoes the step that could have gone wrong.
If you uncheck the component I do not know if the same happens behind the back door.
Other solution: make backup of your project (quartus/project/archive project) and trow it on the forum...
(Not making any promises.)
Best Regards,
Johi.
New ContributorHi Johi,
Well I am finally getting back to this particular FPGA project.
After discovering in my QSYS design that the Timer block was not getting generated (but the other 15 or so QSYS blocks generated OK) I decided to try a fresh, new QSYS design that just has the Clock Source IP and the Timer IP blocks. The clock and reset are hooked up to the Timer and the other Timer ports are exported (see attached). The error report is also attached. The qsys folder and sub-folder directory contents are also attached.
The Timer block works OK with Qsys on my computer at work but for BOTH of my computers at home the same QSYS failure occurs. The computer at work has a Standard Quartus Pro install (v15.1) but the computers at home have the Quartus Pro Lite v15.1.
I have also tried copying the Timer IP (sopc_builder_ip/altera_avalon_timer) from the computer at work into the altera install directory on my home computers.
This is mysterious since all of the other QSYS IP blocks get generated with no problems.
Any other ideas on what to check?
Charles
