QSYS HDL generation error. What is the cause?

Hi Johi,

Thank you very much for your quick response.

I took your advice and I did a fresh install of the Altera_lite v16.0 tools (after uninstalling the Altera tools on my Windows10 computer of course)

After that install I rebuilt my design on a separate drive. Hopefully you can see the screenshot of my Qsys system below with everything connected.

When I compile this I get the same error as before to do with the Timer.

I have captured the executeable line to provide more specifics below:Info: timer_0:

Generation command is [exec C:/altera_lite/16.0/quartus/bin64//perl/bin/perl.exe -I C:/altera_lite/16.0/quartus/bin64//perl/lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin/europa -I C:/altera_lite/16.0/quartus/sopc_builder/bin/perl_lib -I C:/altera_lite/16.0/quartus/sopc_builder/bin -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/common -I C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/altera_lite/16.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=embedded_1_timer_0 {--dir=C:/Users/Charles Pope/AppData/Local/Temp/alt7889_5304015320983038483.dir/0154_timer_0_gen/} --quartus_dir=C:/altera_lite/16.0/quartus --verilog {--config=C:/Users/Charles Pope/AppData/Local/Temp/alt7889_5304015320983038483.dir/0154_timer_0_gen//embedded_1_timer_0_component_configuration.pl} --do_build_sim=0 ]

So I then did as you suggested..... by unchecking the TIMER_0 in the Qsys design and then I reran the QSYS build and everything worked!!!!

So there is clearly something wrong with the timer path I believe. All of the othe components in the altera_lite/16.0.... are found and located and included in the QSYS build.

Below is the altera_lite install library for the sopc_builder_ip:

Any ideas?

Charles