QSYS HDL generation error. What is the cause?

Hello Charles,

I am happy you are one step forward.

What you could try is really remove the timer from your qsys design, recompile, delete the output directory, add it, and recompile again.

The moment you add & compile a component, a copy is made from Intel supplied IP (tcl, vhdl, verilog) to directories of your project directory.

If something is went wrong with this copy process remove & add redoes the step that could have gone wrong.

If you uncheck the component I do not know if the same happens behind the back door.

Other solution: make backup of your project (quartus/project/archive project) and trow it on the forum...

(Not making any promises.)

Best Regards,

Johi.