Problem with SV Interfaces in Quartus

To Quartus' credit, it appears to be complaining about your code before removing the registers.

Warning (12161): Node "my_interface:test_interface|my_interface.some_byte" is stuck at GND because node is in wire loop and does not have a source

Thank you for replying.

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    
    my_interface test_interface();                  //Create an interface instance.
    assign test_byte = test_interface.some_byte;    //Top level output comes from interface.
    
    logic  sample_value;                       //Test "register"
    initial sample_value = 8'b1010_1010;            //Initialize
    assign test_interface.some_byte = sample_value; //Continuous assignment to interface of register value
endmodule

In the examples you showed us, you are not passing the interface through any ports, you are just using it exactly like a module.

That is part of what I’m saying my issues are. I was under the impression that an interface is an entity like a module, not merely a collection of wires. I am specifically trying to use an interface like a module in the examples. I thought that was allowed, and ModelSim was okay with it. I didn't see why it wouldn't be synthesizable that way.

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    //Create an interface instance
    my_interface test_interface();
    
    //Use the interface instance to bridge between two modules
    data_creator m_create(.test_interface);
    pass_through m_pass(.test_interface, .byte_out(test_byte));
endmodule
module data_creator(
    my_interface                test_interface
);
    initial test_interface.some_byte = 8'b1010_1010;
endmodule
module pass_through(
    my_interface                test_interface,
    output  logic          byte_out
);
    assign byte_out = test_interface.some_byte;
endmodule

Possibly review the "Register Power-Up Values in Altera Devices" section of the recommended coding guidelines: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

....
if( ~reset_n ) 
 test_interface.some_byte = 8'b1010_1010;
else 
 test_interface.some_byte = foo;
....

In "Controlling the Power-Up State of Verilog HDL Designs," Altera says:

interface my_interface;
    logic      some_byte;
endinterface
module fpga_tester(
    output  logic          test_byte
);
    //Create an interface instance
    my_interface test_interface();
    
    //Use the interface instance to bridge between two modules
    data_creator m_create(.test_interface, .clk('0), .reset('0));
    pass_through m_pass(.test_interface, .byte_out(test_byte));
endmodule
module data_creator(
    my_interface                test_interface,
    input                       reset,
    input                       clk
);
    always @(posedge clk or posedge reset) begin
        if(reset)   test_interface.some_byte = 8'b1010_1010;    
    end
endmodule
module pass_through(
    my_interface                test_interface,
    output  logic          byte_out
);
    assign byte_out = test_interface.some_byte;
endmodule

Well, going back to the Quartus complaint about no source for the signal, your simplistic example probably just needs ANY driver, reset or otherwise. i.e. you don't need to add the fake reset, just the 'posedge clk' is enough.

interface my_interface;
    logic      some_byte;
    initial some_byte = 8'b1010_1010;
endinterface
module fpga_tester(
	input wire clk,
    output  logic          test_byte
);
    my_interface test_interface();
	
    always @(posedge clk)
	begin
		test_interface.some_byte = test_interface.some_byte + 1'b1;
	end
			
    assign test_byte = test_interface.some_byte;
endmodule

It will be interesting to hear what they say.

interface my_interface;
        logic      some_byte;
	
	function void tick;
		some_byte = some_byte + 1'b1;
	endfunction
	
	function void init;
		some_byte = 8'b1010_1010;
	endfunction
endinterface
module fpga_tester(
	input wire clk,
   output  logic          test_byte
);
	my_interface test_interface();
	counter u0
	(
		.clk ( clk ),
		.x   (test_interface)
	);
			
       assign test_byte = test_interface.some_byte;
endmodule
module counter
(
	input wire clk,
	my_interface x
);
	 initial 
		x.init();
	always @(posedge clk)
		x.tick();
endmodule

I'm the same user writing from a different account. Thank you for putting time into this. It gets a little clearer to me with each new experiment. Your code worked for me, and it led me to realize that Quartus isn't necessarily confused by initial blocks with interfaces. The issue seems to be about the combination of initial blocks specifically with interfaces that don't synthesize into clocked logic. Going back to my first post example, ModelSim and Quartus match in behavior if one simple change is made:

interface my_interface;
    logic      some_byte;
endinterface
module fpga_test(
    input   wire                clk,
    output  logic          test_byte
);
    my_interface test_interface();
    
    assign test_byte = test_interface.some_byte;
    
    initial test_interface.some_byte = 8'b1010_1010;
    always @(posedge clk) test_interface.some_byte <= test_interface.some_byte + 1'd1; //Adding clocked logic here
endmodule

interface my_interface;
    logic      some_byte;
    
    initial some_byte = 8'b1010_1010;
endinterface
module fpga_test(
    input   wire                clk,
    output  logic          test_byte
);
    my_interface test_interface();
    
    assign test_byte = test_interface.some_byte;
    
    always @(posedge clk) test_interface.some_byte <= test_interface.some_byte + 1'd1;
endmodule